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? 1996-2011 microchip technology inc. ds21166k-page 1 24aa52/24lcs52 device selection table features: single supply with operation down to 1.8v low-power cmos technology: - 1 ma active current, typical -1 ? a standby current, typical (i-temp) organized as 1 block of 256 bytes (256 x 8) software write protection for lower 128 bytes hardware write protection for entire array 2-wire serial interface bus, i 2 c? compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz (24aa52) and 400 khz (24lcs52) compatibility self-timed write cycle (including auto-erase) page write buffer for up to 16 bytes esd protection > 4,000v 1,000,000 erase/write cycles data retention > 200 years 8-lead pdip, soic, tssop, msop, dfn and tdfn packages pb-free finishes available available for extended temperature ranges: - industrial (i): -40c to +85c package types description: the microchip technology inc. 24aa52/24lcs52 (24xxx52*) is a 2 kbit electrically erasable prom capable of operation across a broad voltage range (1.8v to 5.5v). this device has a software write-protect feature for the lower half of the array, as well as an external pin that can be used to write-protect the entire array. the software write-protect feature is enabled by sending the device a special command. once this feature has been enabled, it cannot be reversed. in addition to the software protect feature, there is a wp pin that can be used to write-protect the entire array, regardless of whether the software write-protect register has been written or not. this allows the system designer to protect none, half, or all of the array, depending on the application. the device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. low-voltage design permits operation down to 1.8v, with standby and active currents of only 1 ? a and 1 ma, respectively. the 24xxx52 also has a page write capability for up to 16 bytes of da ta. the 24xxx52 is available in the standard 8-pin pdip, surface mount soic, tssop, msop, dfn and tdfn packages. block diagram part number v cc range max clock frequency temp ranges 24aa52 1.8-5.5 400 khz (1) i 24lcs52 2.2-5.5 400 khz i note 1: 100 khz for v cc <2.2v a0a1 a2 v ss 12 3 4 87 6 5 v cc wp scl sda pdip/soic/tssop/msop/dfn/tdfn a0 a1 a2 v ss wp sclsda v cc 87 6 5 1 2 3 4 i/o control logic memory control logic xdec hv generator standard array software write write-protect circuitry ydec v cc v ss sense amp. r/w control sda scl a0 a1 a2 wp protected area (00h-7fh) 2k 2.2v i 2 c ? serial eeprom with software write-protect *24xxx52 is used in this document as a generic part number for the 24aa52/24lcs52 devices. downloaded from: http:///
24aa52/24lcs52 ds21166k-page 2 ? 1996-2011 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 4kv ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to t he device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 1-1: dc specifications dc characteristics v cc = +1.8v to +5.5v industrial (i): t a = -40c to +85c param. no. symbol characteristic min typ max units conditions d1 v ih a0, a1, a2, scl, sda and wp pins d2 high-level input voltage 0.7 v cc v d3 v il low-level input voltage 0.3 v cc v 0.2 v cc for v cc < 2.5v d4 v hys hysteresis of schmitt trigger inputs 0.05 v cc v (note) d5 v ol low-level output voltage 0.40 v i ol = 3.0 ma, v cc = 2.5v d6 i li input leakage current 1 ? av in = v ss or v cc d7 i lo output leakage current 1 ? av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) 1 0p f v cc = 5.0v (note) t a = 25c, f clk = 1 mhz d9 i cc write operating current 1.0 3.0 ma v cc = 5.5v, scl = 400 khz d10 i cc read 0.20 1.0 ma d11 i ccs standby current 0.36 1.0 ? a industrial sda = scl = v cc a0, a1, a2, wp = v ss note: this parameter is periodically sampled and not 100% tested. downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 3 24aa52/24lcs52 table 1-2: ac specifications ac characteristics v cc = +1.8v to +5.5v industrial (i): t a = -40c to +85c param. no. symbol characteristic min typ max units conditions 1f clk clock frequency 400100 khz 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 2t high clock high time 600 4000 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 3t low clock low time 1300 4700 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 4t r sda and scl rise time (note 1) 300 1000 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 5t f sda and scl fall time 300 ns (note 1) 6t hd : sta start condition hold time 600 4000 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 7t su : sta start condition setup time 600 4700 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 8t hd : dat data input hold time 0 n s (note 2) 9t su : dat data input setup time 100 250 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 10 t su : sto stop condition setup time 600 4000 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 11 t aa output valid from clock (note 2) 900 3500 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 12 t buf bus free time: time the bus must be free before a new transmission can start 1300 4700 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 13 t of output fall time from v ih minimum to v il maximum 20 + 0.1 c b 250250 ns 2.2v ? v cc ? 5.5v 1.8v ? v cc ? 2.5v (24aa52) 14 t sp input filter spike suppression (sda and scl pins) 50 ns (note 1 and note 3) 15 t wc write cycle time (byte or page) 5m s 16 endurance 1m cycles 25c, v cc = 5.0v (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endu rance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips web site at www.microchip.com. downloaded from: http:///
24aa52/24lcs52 ds21166k-page 4 ? 1996-2011 microchip technology inc. figure 1-1: bus timing data figure 1-2: bus timing start/stop 7 5 2 4 8 9 10 12 11 14 6 scl sda in sda out 3 7 6 d4 10 start stop scl sda downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 5 24aa52/24lcs52 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 a0, a1, a2 the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 24xxx52 devices may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v ss or v cc . 2.2 serial address/data input/output (sda) this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal. therefore, the sda bus requires a pull- up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. 2.4 write-protect (wp) this is the hardware write-protect pin. it can be tied to v cc or v ss . if tied to v cc , the hardware write protection is enabled. if the wp pin is tied to v ss , the hardware write protection is disabled. symbol pdip soic tssop msop dfn (1) tdfn (1) description a0 1 1 1 1 1 1 chip address input a1 2 2 2 2 2 2 chip address input a2 3 3 3 3 3 3 chip address input v ss 4 44444 g r o u n d sda 5 5 5 5 5 5 serial address/data i/o scl 6 6 6 6 6 6 serial clock wp 7 7 7 7 7 7 write-protect input v cc 8 8 8 8 8 8 +1.8v to 5.5v power supply note 1: the exposed pad on the dfn/tdfn packages can be connected to v ss or left floating. downloaded from: http:///
24aa52/24lcs52 ds21166k-page 6 ? 1996-2011 microchip technology inc. 3.0 functional description the 24xxx52 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data, as a receiver. the bus has to be controlled by a master device, which generates the serial clock (scl), controls the bus access and gener- ates the start and stop conditions, while the 24xxx52 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited; although only the last sixteen will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first-in, first-out (fifo) fashion. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end-of- data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xxx52) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus note: the 24xxx52 does not generate any acknowledge bits if an internal programming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 7 24aa52/24lcs52 4.6 device addressing a control byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit control code which is set to 1010 for normal read and write operations and 0110 for writing to the write-protect register. the control byte is followed by three chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24xxx52 devices on the same bus and are used to determine which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. the device will not acknowl- edge if you attempt a read command with the control code set to 0110 . the eighth bit of slave address determines if the master device wants to read or write to the 24xxx52 (figure 4-2). when set to a one, a read operation is selected. when set to a zero, a write operation is selected. figure 4-2: control byte allocation 5.0 write operations 5.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit, which is a logic low, are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow, once it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24xxx52. after receiving another acknowledge signal from the 24xxx52, the master device will transmit the data word to be written into the addressed memory location. the 24xxx52 acknowledges again and the master gener- ates a stop condition. this initiates the internal write cycle, which means that during this time, the 24xxx52 will not generate acknowledge signals (figure 5-1). if an attempt is made to write to the array when the soft- ware or hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. the write cycle time must be observed even if the write protection is enabled. 5.2 page write the write control byte, word address and the first data byte are transmitted to the 24xxx52 in the same way as in a byte write. instead of generating a stop condi- tion, the master transmits up to 15 additional data bytes to the 24xxx52, which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. upon receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin (figure 5-2). if an attempt is made to write to the array when the hardware write protection has been enabled, the device will acknowl- edge the command, but no data will be written. the write cycle time must be observed even if the write protection is enabled. operation control code chip select r/w read 1010 a2 a1 a0 1 write 1010 a2 a1 a0 0 set write-protect register 0110 a2 a1 a0 0 or start read/write slave address r/w a 1 0 1 0 a2 a1 a0 0 1 1 0 a2 a1 a0 note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or page size) and end at addresses that are integer mul- tiples of [page size C 1]. if a page write command attempts to write across a phys- ical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. downloaded from: http:///
24aa52/24lcs52 ds21166k-page 8 ? 1996-2011 microchip technology inc. figure 5-1: byte write figure 5-2: page write s p bus activity master sda line bus activity st a r t st o p control byte word address data ac k ac k ac k s p bus activity master sda line bus activity st a r t control byte word address (n) data (n) data (n + 15) st o p ac k ac k ac k ac k ac k data (n + 1) downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 9 24aa52/24lcs52 6.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 6-1 for flow diagram. figure 6-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes downloaded from: http:///
24aa52/24lcs52 ds21166k-page 10 ? 1996-2011 microchip technology inc. 7.0 write protection the 24xxx52 has a software write-protect feature that allows the lower half of the array (addresses 00h-7fh) to be permanently write-protected, as well as a wp pin that can be used to protect the entire array. 7.1 software write-protect the software write-protect feature is invoked by writing to the write-protect register. this is done by sending a command similar to a normal write command. as shown in figure 7-1, the write-protect register is written by sending a write command with the slave address set to 0110 instead of 1010 and the address bits and data bits are dont cares. once the software write-protect register has been written, the device will not acknowledge the 0110 control byte. figure 7-1: setting write-protect register 7.2 resetting the software write-protect fuse it is possible to reset the software write-protect feature on the 24xxx52. this is done by sending a command similar to setting the software write-protect command, except the command is sent before the regular control byte and is 1001 . the full command will be shown in figure 7-2. in order for the command to work, a voltage of vcc + 5.5v must be applied to the wp pin and must be sustained for 1 ? s before the command is given. the customer should also allow for a 5 ms delay after the stop bit for t wc . s p bus activity master sda line bus activity st a r t st o p control byte word address data ac k ac k ac k 00 1 1 downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 11 24aa52/24lcs52 figure 7-2: resetting write-protect fuse (rwpf) 7.3 hardware write-protect the wp pin can be tied to v cc or v ss . if tied to v cc , the entire array will be write-protected, regardless of whether the software write-protect register has been written or not. if the wp pin is set to v cc , it will prevent the software write-protect register from being written. if the wp is tied to v ss , write protection is determined by the status of the software write-protect register for addresses 00h-7fh. addresses 80h-ffh are solely protected by the wp pin level. 101 bus activity master sda line bus activity st a r t word address (0x09) data (0xff) st o p ac k ac k ac k s 1001 p 0 wp = v hh = v cc + 5.5v 000 00001 0 01111111 11 rwpf command control byte 0 t wc 1 ? s 000 note: clock = 100 khz, v dd = 1.8v to 5.5v downloaded from: http:///
24aa52/24lcs52 ds21166k-page 12 ? 1996-2011 microchip technology inc. 8.0 read operation read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to 1 . there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24xxx52 contains an address counter that maintains the address of the last word accessed, inter- nally incremented by 1 . therefore, if the previous access (either a read or write operation) was to address n , the next current address read operation would access data from address n+1 . upon receipt of the slave address with r/w bit set to 1 , the 24xxx52 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24xxx52 discontinues transmission (figure 8-1). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 24xxx52 as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a 1 . the 24xxx52 then issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24xxx52 discontinues transmission (figure 8-2). 8.3 sequential read sequential reads are initiated in the same way as a random read, with the exception that after the 24xxx52 transmits the first data byte, the master issues an acknowledge, as opposed to a stop condition in a random read. this directs the 24xxx52 to transmit the next sequentially addressed 8-bit word (figure 8-3). to provide sequential reads, the 24xxx52 contains an internal address pointer, which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 8.4 contiguous addressing across multiple devices the chip select bits (a2, a1, a0) can be used to expand the contiguous address space for up to 16k bits by adding up to eight 24xxx52 devices on the same bus. in this case, software can use a0 of the control byte as address bit a8; a1 as address bit a9, and a2 as address bit a10. it is not possible to sequentially read across device boundaries. 8.5 noise protection and brown-out the 24xxx52 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5v at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. figure 8-1: current address read sp bus activity master sda line bus activity st o p control byte data (n) ac k no a c k st a r t downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 13 24aa52/24lcs52 figure 8-2: random read figure 8-3: sequential read s p s bus activity master sda line bus activity st a r t st o p control byte ac k word address (n) control byte st a r t data (n) ac k ac k n o a c k p bus activity master sda line bus activity st o p control byte ac k n o a c k data (n) data (n + 1) data (n + 2) data (n + x) ac k ac k ac k downloaded from: http:///
24aa52/24lcs52 ds21166k-page 14 ? 1996-2011 microchip technology inc. 9.0 packaging information 9.1 package marking information xxxxxxxxtxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxt xxxxyyww nnn 24aa52 i/p 3ec 0510 24lcs52i sn 0510 3ec 8-lead msop example: xxxxxt ywwnnn 4s52i 5103ec 8-lead tssop example: xxxx tyww nnn s52 i510 3ec 8-lead 2x3 dfn xxx yww nn example: 3 e 3 e 2m4 510 3e 8-lead 2x3 tdfn xxx yww nn example: am4 510 3e downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 15 24aa52/24lcs52 legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e * standard otp marking consists of microchip part number, year code, week code, and traceability code. note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. part number 1st line marking codes tssop msop dfn tdfn 24aa52 a52 4a52i 2m1 am1 24lcs52 s52 4s52i 2m4 am4 downloaded from: http:///
24aa52/24lcs52 ds21166k-page 16 ? 1996-2011 microchip technology inc. n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 17 24aa52/24lcs52 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa52/24lcs52 ds21166k-page 18 ? 1996-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 19 24aa52/24lcs52 downloaded from: http:///
24aa52/24lcs52 ds21166k-page 20 ? 1996-2011 microchip technology inc. d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 21 24aa52/24lcs52 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa52/24lcs52 ds21166k-page 22 ? 1996-2011 microchip technology inc. d n e e1 note 1 1 2 e b a a1 a2 c l1 l downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 23 24aa52/24lcs52 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa52/24lcs52 ds21166k-page 24 ? 1996-2011 microchip technology inc. d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 25 24aa52/24lcs52 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa52/24lcs52 ds21166k-page 26 ? 1996-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 27 24aa52/24lcs52 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa52/24lcs52 ds21166k-page 28 ? 1996-2011 microchip technology inc. downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 29 24aa52/24lcs52 appendix a: revision history revision g added 2.2v to document; revised features section to include standard and pb-free finishes. corrections to section 1.0, electrical characteristics; product id system, added lead finish info. revision h added reset software write-protect feature. added 2x3 dfn package option. revision j revised sections 6.3 and 8.4. revised dfn package drawing. revision k (11/2011) added tdfn package. downloaded from: http:///
24aa52/24lcs52 ds21166k-page 30 ? 1996-2011 microchip technology inc. notes: downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 31 24aa52/24lcs52 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
24aa52/24lcs52 ds21166k-page 32 ? 1996-2011 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in whic h our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21166k 24aa52/24lcs52 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page33 24aa52/24lcs52 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. part no. x /xx package temperature range device device: 24aa52: = 1.8v, 2 kbit i 2 c serial eeprom 24aa52t: = 1.8v, 2 kbit i 2 c serial eeprom (tape and reel) 24lcs52: = 2.2v, 2 kbit i 2 c serial eeprom 24lcs52t: = 2.2v, 2 kbit i 2 c serial eeprom (tape and reel) temperature range: i = -40c to +85c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = plastic tssop (4.4 mm), 8-lead ms = plastic micro small outline (msop), 8-lead mc = micro lead frame (2x3 mm body), 8-lead mny (1) = tdfn (2x3x0.75 mm body), 8-lead (tape and reel only) note 1: "y" indicates a nickel palladium gold (nipdau) finish. examples: a) 24aa52-i/p: industrial temperature, 1.8v, pdip package b) 24aa52-i/sn: industrial temperature, 1.8v, soic package c) 24aa52t-i/ms: tape and reel, industrial temperature, 1.8v, msop package d) 24lcs52-i/p: industrial temperature, 2.2v, pdip package e) 24lcs52-i/mc: industrial temperature, 2.2v, dfn package f) 24lcs52t-i/ms: tape and reel, industrial temperature, 2.2v, msop package g) 24lcs52t-i/mny: tape and reel, indus- trial temperature, 2.2v, tdfn package x lead finish downloaded from: http:///
24aa52/24lcs52 ds21166k-page 34 ? 1996-2011 microchip technology inc. notes: downloaded from: http:///
? 1996-2011 microchip technology inc. ds21166k-page 35 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 1996-2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-786-7 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
ds21166k-page 36 ? 1996-2011 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 08/02/11 downloaded from: http:///

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